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power management & multimarket data sheet revision 1.3, 2015-07-16 final esd5v5u5ulc ultra-low capacitance esd / tran sient / surge protection array esd5v5u5ulc tvs diodes transient voltage suppressor diodes
edition 2015-07-16 published by infineon technologies ag 81726 munich, germany ? 2015 infineon technologies ag all rights reserved. legal disclaimer the information given in th is document shall in no event be rega rded as a guarantee of conditions or characteristics. with respect to any ex amples or hints given herein, any typi cal values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including wit hout limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ) warnings due to technical requirements, components may contain dangerous substances. for in formation on the types in question, please contact the neares t infineon technologies office. infineon technologies components may be used in life-suppo rt devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or sys tem. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if t hey fail, it is reasonable to assume that the health of the user or other persons may be endangered.
esd5v5u5ulc final data sheet 3 revision 1.3, 2015-07-16 trademarks of infineon technologies ag aurix?, bluemoon?, comneon? , c166?, crossave?, canpak?, ci pos?, coolmos?, coolset?, corecontrol?, dave?, easypim?, econobridg e?, econodual?, eco nopack?, econopim?, eicedriver?, eupec?, fcos?, hitfet?, hybridpack?, isoface? , i2rf?, isopack?, mipaq?, modstack?, my-d?, novalithic?, omnitune?, optimos?, origa?, profet?, pro-sil?, primarion?, primepack? , rasic?, reversave?, satric?, sieget?, sindrion ?, smarti?, smartlewis?, tempfet?, thin q!?, tricore?, trenchstop?, x-gold?, xmm?, x-pmu?, xposys?. other trademarks advance design system? (ads) of agilent tech nologies, amba?, arm?, multi-ice?, primecell?, realview?, thumb? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat-iq? of dect forum. colossus? , firstgps? of trimble navigation ltd. emv? of emvco, llc (visa holdings inc.). epco s? of epcos ag. flexgo? of microsoft corporation. flexray? is licensed by flexra y consortium. hyperterminal? of hilgraeve incorpor ated. iec? of commission electrotechnique internationale. irda? of infrared data association corporation. iso? of international organization for standardization . matlab? of mathworks, inc. maxim? of maxim integrated products, inc. mi crotec?, nucleus? of mentor graphi cs corporation. mifare? of nxp. mipi? of mipi alliance, inc. mips? of mips technologies, in c., usa. murata? of murata manufacturing co., microwave office? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc. openwave? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of si rius sattelite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of symbian software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. tektro nix? of tektronix inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilo g?, palladium? of cadence design systems, inc. vlynq? of texas instruments incorpor ated. vxworks?, wind river? of wind ri ver systems, inc. zetex? of diodes zetex limited. last trademarks update 2010-06-09 revision history: rev. 1.2, 2013-02-07 page or item subjects (major changes since previous revision) revision 1.3, 2015-07-16 14 marking drawing updated
esd5v5u5ulc ultra-low capacitance esd / transient / surge protection array final data sheet 4 revision 1.3, 2015-07-16 1 ultra-low capacitance esd / tran sient / surge protection array 1.1 features ? esd / transient protection of high speed data lines exceeding ? iec61000-4-2 (esd): 25 kv (air / contact) ? iec61000-4-4 (eft): 2.5 kv / 50 a (5/50 ns) ? iec61000-4-5 (surge): 6 a (8/20 s) ? maximum working voltage: v rwm = 5.5 v ? extremely low capacitance c l = 0.45 pf i/o to gnd (typical) ? very low dynamic resistance: r dyn i/o to gnd = 0.2 ? (typical) ? very low reverse clamping voltage: v cl = 9 v (typical) at i pp = 16 a ? protection of v bus with one line freely selectable ? pb-free (rohs compliant) package 1.2 application examples ? protection of all i/o and v bus lines in dual usb2.0 ports ? 10/100/100 ethernet ? dvi, hdm, firewire 1.3 product description figure 1 pin configuration and schematic diagram table 1 ordering information type package configuration marking code esd5v5u5ulc sc74 5 lines, uni-directional 20 esd5v5u5ulc_pinconf_and_schematicdiag.vsd sc74 pin 2 pin 3 pin 6pin 5pin 4 pin 1 a) pin configuration b) schematic diagram pin 5 pin 1 pin 3 pin 4 pin 2 gnd pin 6
esd5v5u5ulc characteristics final data sheet 5 revision 1.3, 2015-07-16 2 characteristics attention: stresses above the max. values listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 2.1 electrical characteristics at t a = 25 c, unless ot herwise specified figure 2 definitions of electrical characteristics [1] table 2 maximum rating at t a = 25 c, unless otherwise specified parameter symbol values unit min. typ. max. esd contact discharge 1) 1) v esd according to iec61000-4-2 v esd -25 ? 25 kv peak pulse current ( t p = 8/20 s) 2) 2) i pp according to iec61000-4-5 i pp -6 ? 6 a operating temperature range t op -40 ? 125 c storage temperature t stg -65 ? 150 c

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esd5v5u5ulc characteristics final data sheet 6 revision 1.3, 2015-07-16 table 3 dc characteristics at t a = 25 c, unless otherwise specified parameter symbol values unit note / test condition min. typ. max. reverse working voltage v rwm ? ? 5.5 v i/o to gnd reverse current i r ? <1 100 na v r = 5.5 v, i/o to gnd table 4 rf characteristics at t a = 25 c, unless otherwise specified parameter symbol values unit note / test condition min. typ. max. line capacitance c l ?0.451pf v r = 0 v, f = 1 mhz, i/o to gnd ?0.230.5pf v r = 0 v, f = 1 mhz, i/o to i/o line capacitance c l ?0.25?pf v r = 0 v, f = 825 mhz, i/o to gnd ?0.13?pf v r = 0 v, f = 825 mhz, i/o to i/o capacitance variation between i/o and gnd ? c i/o-gnd ?0.02?pf v r = 0 v, f = 1 mhz, i/o to gnd capacitance variation between i/o ? c i/o-i/o ?0.01?pf v r = 0 v, f = 1 mhz, i/o to i/o
esd5v5u5ulc characteristics final data sheet 7 revision 1.3, 2015-07-16 table 5 esd characteristics at t a = 25 c, unless otherwise specified parameter symbol values unit note / test condition min. typ. max. reverse clamping voltage 1) 1) i pp according to iec61000-4-5 v cl ?9?v i pp = 1 a, t p = 8/20 s, i/o pin to gnd ?12?v i pp = 3 a, t p = 8/20 s, i/o pin to gnd reverse clamping voltage 2) [2] v cl ?8.9?v i pp = 16 a, t p = 100 ns, i/o pin to gnd ?11.5?v i pp = 30 a, t p = 100 ns, i/o pin to gnd forward clamping voltage 1) v fc ?1.75?v i pp = 1 a, t p = 8/20 s, gnd pin to i/o ?2.5?v i pp = 3 a, t p = 8/20 s, gnd pin to i/o forward clamping voltage 2) [2] v fc ?5.4?v i pp = 16 a, t p = 100 ns, gnd pin to i/o ?9.2?v i pp = 30 a, t p = 100 ns, gnd pin to i/o dynamic resistance i/o to gnd 2) [2] 2) please refer to application note an210 [2] . tlp parameter: z 0 = 50 , t p = 100ns, t r = 300ps, averaging window: t 1 = 30 ns to t 2 = 60 ns, extraction of dynamic resistance using least squares fit of tlp charactertistic between i pp1 = 10 a and i pp2 = 40 a. r dyn, i/o to gnd ?0.2? dynamic resistance gnd to i/o 2) [2] r dyn, gnd to i/o ?0.3?
esd5v5u5ulc characteristics final data sheet 8 revision 1.3, 2015-07-16 2.2 typical characteristics at t a = 25 c, unless otherwise specified figure 3 line capacitance c l = f ( v r ) at f = 825 mhz figure 4 line capacitance c l = f ( f ), v r = 0 v 0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 c l [pf] v r [v] 0 0.1 0.2 0.3 0.4 0.5 0.6 10 6 10 7 10 8 10 9 10 10 c l [pf] f [hz] i/o to gnd i/o to i/o
esd5v5u5ulc characteristics final data sheet 9 revision 1.3, 2015-07-16 figure 5 insertion loss i l = f ( f ), v r = 0 v figure 6 forward characteristic, i f = f ( v f ), current forced -20 -15 -10 -5 0 10 5 10 6 10 7 10 8 10 9 10 10 - | s 21 | 2 [db] f [hz] 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 0 0.5 1 i f [a] v f [v]
esd5v5u5ulc characteristics final data sheet 10 revision 1.3, 2015-07-16 figure 7 reverse current i r = f ( t a ), v r = 5.5 v (typical) figure 8 reverse characteristic, i r = ( v r ), voltage forced 10 -12 10 -11 10 -10 10 -9 10 -8 10 -7 -50 -25 0 25 50 75 100 125 150 i r [a] t a [ c] 10 -12 10 -11 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 10 -3 0 5 10 i r [a] v r [v]
esd5v5u5ulc characteristics final data sheet 11 revision 1.3, 2015-07-16 figure 9 tlp characteristic i/o to gnd note: [2] figure 10 tlp characteristic gnd to i/o note: [2] note: tlp parameter: z 0 = 50 , t p = 100 ns, t r = 300 ps, averaging window: t 1 = 30 ns to t 2 = 60 ns, extraction of dynamic resistance using least squares fit of tlp charactertistic between i pp1 = 10 a and i pp2 = 40 a. the equivalent stress level v iec according iec 61000-4-2 ( r = 330 , c = 150 pf) is calculated at the broad peak of the iec waveform at t = 30 ns with 2 a / kv 0 10 20 30 40 50 60 5 10 15 20 25 0 5 10 15 20 25 30 i tlp [a] equivalent v iec [kv] v tlp [v] esd5v5u5ulc r dyn r dyn =0.2 0 10 20 30 40 50 60 5 10 15 20 25 0 5 10 15 20 25 30 i tlp [a] equivalent v iec [kv] v tlp [v] esd5v5u5ulc r dyn r dyn =0.3
esd5v5u5ulc application information final data sheet 12 revision 1.3, 2015-07-16 3 application information figure 11 ethernet figure 12 usb2.0 esd5v5u5ulc_ethernet_application .vsd 1 : 1 1 : 1 quad transformer rj45 ethernet connector primary esd current secondary esd current rx1 tx1 secondary esd/surge protection gigabit ethernet transceiver (phy) 75 ohm res common 2nf cap res host ethernet cable twisted pair 1 : 1 1 : 1 quad transformer rj45 ethernet connector primary esd current secondary esd current 75 ohm res common 2nf cap res device line-pair #1 line-pair #2 line-pair #3 line-pair #4 line-pair #1 line-pair #2 line-pair #3 line-pair #4 rx1 tx1 secondary esd/surge protection gigabit ethernet transceiver (phy) esd5v5u5ulc_usb20_application .vsd d1+ usb2.0 cable#1 usb2.0 host1 ls/fs/hs data #1 in / out d1- usb2.0 host2 ls/fs/hs vcc gnd vcc d2- d+ d- d+ d- tvs esd diodes array d2+ vcc gnd d1+ usb2.0 device1 ls/fs/hs d1- usb2.0 device2 ls/fs/hs vcc d2- d2+ usb2.0 cable#2 data #2 in / out data #1 in / out data #2 in / out host controller d+ d- d+ d- usbconnectors tvs esd diodes array device controller
esd5v5u5ulc ordering information scheme (examples) final data sheet 13 revision 1.3, 2015-07-16 4 ordering information scheme (examples) figure 13 ordering information scheme esd 5v3 u - xx yy package or application xx = pin number (i.e.: 02 = 2 pins; 03 = 3 pins) yy = package family: ls = tsslp lrh = tslp s = sot363 u = sc74 xx = application family: lc = low clamp hdmi u ni- / b i-directional or r ail to r ail protection maximum working voltage v rwm in v: (i.e.: 5v3 = 5.3v) esd 0p1 rf - xx yy package xx = pin number (i.e.: 02 = 2 pins; 03 = 3 pins) yy = package family: ls = tsslp lrh = tslp for r adio f requency applications line capacitance c l in pf: (i.e.: 0p1 = 0.1pf) n u n umber of protected lines (i.e.: 1 = 1 line; 4 = 4 lines) capacitance: s tandard (>10pf), l ow (<10pf), u ltra-low (<1pf)
esd5v5u5ulc package information final data sheet 14 revision 1.3, 2015-07-16 5 package information 5.1 pg-sc74 (mm) figure 14 pg-sc74: package overview figure 15 pg-sc74: footprint figure 16 pg-sc74: packing figure 17 pg-sc74: marking (example) sc74-po v0 4 54 6 3 2 1 1.1 max. (0.35) (2.25) 0.2 2.9 b 0.2 +0.1 -0.05 0.35 pin 1 marking m b 6x 0.95 1.9 0.15 -0.06 +0.1 1.6 a 0.1 2.5 0.25 0.1 0.1 a 0.2 m 0.1 max. 0.5 0.95 1.9 2.9 sc74-fpr v0 4 sc74-t p 2.7 4 3.15 pin 1 marking 8 0.2 1.15 sc74-mk v04 manufacturer 2005, june date code (ym) bcw66h type code pin 1 marking laser marking
esd5v5u5ulc references final data sheet 15 revision 1.3, 2015-07-16 references [1] on-chip esd protection for integrated circuits , albert z. h. wang, isbn:0-7923-7647-1 [2] infineon technologie ag - application note an210 : effective esd protection design at system level using vf-tlp characterization methodology
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